The present invention relates to improvements for transistors such as junction FETs (JFETs) and static induction transistors (SITs).
Silicon carbide (SiC) has about 10 times as high a dielectric breakdown field as silicon (Si), so that a drift region provided to maintain a blocking voltage can be made thin and highly concentrated, thus reducing losses. Power semiconductor devices using SiC include junction FETs (JFETs) and static induction transistors (SITs).
An example of an SIT that takes advantage of the features of SiC is described in JP-A-2001-94120. The structure in this Japanese patent has an n+ drain region, an n− drift region, an n+ source region, a p-type gate region and a p+ contact region. It also has a drain electrode, a source electrode and a gate electrode.
SIT are transistors that turns an electric current on or off by a depletion layer expanding from the gate into a channel. By narrowing the channel width, which is equivalent to an interval between the p-type gate regions, a normally-off capability to maintain an off-state is realized even when a gate voltage is 0 V. The channel is an area between the p-type gate regions, and a thickness of the p-type gate regions represents a channel length. In the p-type gate region, the depletion layer spreading from the shallow contact region toward the n−-type drift region is not involved in the current control. When an impurity concentration in the p-type gate regions on each side of the channel is low, since the depletion layer expands not only on the channel side but also in the p-type region, a drain voltage blocking effect is weak during the off-state. Therefore, the channel needs to be formed to have an extremely fine width to realize a high blocking voltage.
More specifically, let us consider a case of an SIT with a blocking voltage of several hundred volts. If the thickness of the p-type gate region or the channel length is about 0.5 μm, the channel width needs to be 0.3 μm or less to secure an on-state interruption capability. The p-type gate region requires a junction depth of about 1 μm. To obtain a junction of such a depth, ion implantation must be performed with a large acceleration energy. It is conceivable to use an energy as high as a MeV level in the ion implantation. Such a high energy ion implantation, however, requires a thick mask material for shielding, so that for a fine channel it is necessary to form a fine line with a large aspect ratio with a photolithography process, making the formation of fine channels more susceptible to process variations. If we take process variations to be ±0.05 μm, the on-state voltage and the blocking voltage are both susceptible to the effect of the process variations, resulting in characteristic variations including a desired blocking voltage failing to be produced or a current failing to flow even during the on-state due to a too narrow channel.